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INTEGRATED CIRCUITS
DATA SHEET
UDA1360TS Low-voltage low-power stereo audio ADC
Preliminary specification Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC01 2000 Feb 08
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
FEATURES General * Low power consumption * 2.4 to 3.6 V power supply * Supports 256 and 384fs system clock * Supports sampling frequency range of 5 to 55 kHz * Small package size (SSOP16) * Integrated high-pass filter to cancel DC offset * Power-down mode * Supports 2 V (RMS) input signals * Easy application * Non-inverting ADC plus decimation filter. Multiple format output interface * I2S-bus and MSB-justified format compatible * Up to 20 significant bits serial output. Advanced audio configuration * Stereo single-ended input configuration * High linearity, dynamic range and low distortion. QUICK REFERENCE DATA SYMBOL Supplies VDDA VDDD IDDA IDDD Tamb ADC Vi(rms) (THD + N)/S S/N cs input voltage (RMS value) total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio channel separation see Table 1 at 0 dB at -60 dB; A-weighted VI = 0 V; A-weighted - - - - - 1.0 -85 -37 97 100 analog supply voltage digital supply voltage analog supply current digital supply current operating ambient temperature 2.4 2.4 - - -40 3.0 3.0 9 3.5 - PARAMETER CONDITIONS MIN. TYP. GENERAL DESCRIPTION
UDA1360TS
The UDA1360TS is a single chip stereo Analog-to-Digital Converter (ADC) employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording functions. The UDA1360TS supports the I2S-bus data format and the MSB-justified data format with word lengths of up to 20 bits.
MAX.
UNIT
3.6 3.6 - - +85 - -80 -33 - -
V V mA mA C V dB dB dB dB
ORDERING INFORMATION TYPE NUMBER UDA1360TS 2000 Feb 08 PACKAGE NAME SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm 2 VERSION SOT369-1
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
BLOCK DIAGRAM
UDA1360TS
handbook, full pagewidth
VDDA 16
VSSA 15
Vref(p) Vref(n) 5 4
Vref 2
UDA1360TS
1 ADC () 8 DECIMATION FILTER 3 ADC () CLOCK CONTROL 14 7 SYSCLK FSEL PWON
VINL
VINR
DATAO BCK WS
13 11 12 DIGITAL INTERFACE DC-CANCELLATION FILTER 9 10 VDDD VSSD
6
MGM967
SFOR
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
PINNING SYMBOL VINL Vref VINR Vref(n) Vref(p) SFOR PWON SYSCLK VDDD VSSD BCK WS DATAO FSEL VSSA VDDA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION left channel input reference voltage right channel input ADC negative reference voltage ADC positive reference voltage data format selection input power control input system clock input 256 or 384fs digital supply voltage digital ground bit clock input word selection input data output system clock frequency select analog ground analog supply voltage
handbook, halfpage
UDA1360TS
VINL 1 Vref 2 VINR 3 Vref(n) 4
16 VDDA 15 VSSA 14 FSEL 13 DATAO
UDA1360TS
Vref(p) 5 SFOR 6 PWON 7 SYSCLK 8
MGM968
12 WS 11 BCK 10 VSSD 9 VDDD
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION System clock The UDA1360TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable via the static FSEL pin, and the system clock must be locked in frequency to the digital interface input signals. The options are 256fs (FSEL = LOW) and 384fs (FSEL = HIGH). The sampling frequency range is 5 to 55 kHz. The BCK clock can be up to 128fs, or in other words the BCK frequency is 128 times the Word Select (WS) frequency or less: fBCK 128 x fWS. Notes: 1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface. 2. For MSB justified formats it is important to have a WS signal with 50% duty factor. Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1360TS consists of two 3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128. Input level The overall system gain is proportional to VDDA. The 0 dB input level is defined as that which gives a -1 dB FS digital output (relative to the full-scale swing). In addition, an input gain switch is incorporated with the above definitions. The UDA1360TS front-end is equipped with a selectable 0 or 6 dB gain, in order to supports 2 V (RMS) input using a series resistor of 12 k. For the definition of the pin settings for 1 or 2 V (RMS) mode given in Table 1, it is assumed that this resistor is present as a default component. If the 2 V (RMS) signal input is not needed, the external resistor should not be used.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
Table 1 Application modes using input gain stage INPUT GAIN SWITCH 0 dB 6 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS) Mute
UDA1360TS
RESISTOR (12 k) Present Present Absent Absent
On recovery from power-down, the serial data output DATAO is held LOW until valid data is available from the decimation filter. This time tracks with the sampling frequency: 12288 t = --------------- = 279 ms ; where fs = 44.1 kHz. fs Power-down mode The PWON pin can control the power saving together with the optional gain switch for 2 V (RMS) or 1 V (RMS) input. When the PWON pin is set LOW, the ADC is set to power-down. When PWON is set to HIGH or to half the power supply, then either 6 dB gain or 0 dB gain in the analog front-end is selected. Application modes The UDA1360TS can be set to different modes using two 3-level pins and one 2-level pin. The selection of modes is given in Table 3. Table 3 PIN SFOR PWON FSEL Mode selection summary VSS I2S-bus 256fs
1 V 2 DD
Multiple format output interface The UDA1360TS supports the following data output formats; * I2S-bus with data word length of up to 20 bits * MSB-justified serial format with data word length of up to 20 bits. The output format can be set by the static SFOR pin. When SFOR is LOW, the I2S-bus is selected, when SFOR is set HIGH the MSB-justified format is selected. The data formats are illustrated in Fig.4. Left and right data channel words are time multiplexed. Decimation filter The decimation from 128fs is performed in two stages. The first stage realizes 3rd-order sin x/x characteristic. This filter decreases the sample rate by 16. The second stage (an FIR filter) consists of 3 half-band filters, each decimating by a factor of 2. Table 2 DC cancellation filter characteristics ITEM Pass-band ripple Pass-band gain Stop band Droop Attenuation at DC Dynamic range >0.55fs at 0.00045fs at 0.00000036fs 0 to 0.45fs CONDITION VALUE (dB) none 0 -60 0.031 >40 >110
VDD MSB 6 dB gain 384fs
test mode -
power-down 0 dB gain
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
UDA1360TS
handbook, full pagewidth
WS
tBCK(H) tr BCK tf th;WS
ts;WS
tBCK(L) Tcy
td;DAT(WS)
td;DAT th;DAT
DATAO
MGM969
Fig.3 Serial interface timing.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground, VDDD = VDDA = 3 V; Tamb = 25 C; unless otherwise specified. SYMBOL VDDD VDDA Txtal(max) Tstg Tamb Ves PARAMETER digital supply voltage analog supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 2 note 3 Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient VALUE in free air VALUE 140 UNIT K/W CONDITIONS note 1 note 1 - - - -65 -40 -3000 -300 MIN. MAX. 5.0 5.0 150 +125 +85 +3000 +300 V V C C C V V UNIT
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
UDA1360TS
DC CHARACTERISTICS VDDD = VDDA = 3 V; Tamb = 25 C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA IDDD Digital inputs PINS BCK, FSEL, SYSCLK AND WS VIH VIL ILI CI VIH VIM VIL VOH VOL Analog Vref RI CI Note 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. reference voltage input resistance input capacitance referenced to VSSA 0.45VDDA - - 0.5VDDA 12 20 0.55VDDA - - V k pF HIGH-level input voltage LOW-level input voltage input leakage current input capacitance 0.8VDDD -0.5 - - 0.8VDDD 0.3VDDD -0.5 IOH = -2 mA IOL = 2 mA 0.85VDDD - - - - - - - - - - VDDD + 0.5 0.2VDDD 10 10 V V A pF analog supply voltage digital supply voltage analog supply current digital supply current note 1 note 1 operation mode power-down mode operation mode power-down mode 2.4 2.4 - - - - 3.0 3.0 9 3.5 3.5 0.5 3.6 3.6 - - - - V V mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
PINS PWON AND SFOR HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage VDDD + 0.5 0.7VDDD 0.2VDDD - 0.4 V V V
Digital output; Pin DATAO HIGH-level output voltage LOW-level output voltage V V
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3 V; fi = 1 kHz; Tamb = 25 C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL Vi(rms) Vi (THD + N)/S S/N cs PSRR PARAMETER input voltage (RMS value) unbalance between channels total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio channel separation power supply rejection ratio at 0 dB at -60 dB; A-weighted VI = 0 V; A-weighted CONDITIONS see Table 1 TYP. 1.0 0.1 -85 -37 97 100 30 - -
UDA1360TS
MAX. V
UNIT dB dB dB dB dB dB
-80 -33 - - -
AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.7 to 3.6 V; Tamb = -20 to +85 C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL Timing Tsys tCWL tCWH Tcy tBCK(H) tBCK(L) tr tf td;DAT td;DAT(WS) th;DAT ts;WS clock cycle fsys LOW-level pulse width fsys HIGH-level pulse width bit clock cycle bit clock HIGH time bit clock LOW time rise time fall time data output delay time (from BCK falling edge) data output delay time (from WS edge) data output hold time word selection set-up time MSB-justified format fsys = 256fs fsys = 384fs 71 47 0.4Tsys 0.4Tsys
1 64fs
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
89 59 - - - - - - - - - - -
782 522 0.6Tsys 0.6Tsys - - - 20 20 80 80 - -
ns ns ns ns
Serial data timing (see Fig.3) ns ns ns ns ns ns ns ns ns 100 100 - - - - 0 20
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WS 1 BCK 2 LEFT 3 8 1 2 DATA MSB B2
Philips Semiconductors
LSB
handbook, full pagewidth
Low-voltage low-power stereo audio ADC
RIGHT 3 8
MSB
B2 I2S-BUS FORMAT
LSB
MSB
9
WS 1 BCK 2 LEFT 3 8 1 2 RIGHT 3 8 DATA MSB B2 LSB MSB B2 MSB-JUSTIFIED FORMAT LSB MSB B2
MGM970
Preliminary specification
UDA1360TS
Fig.4 Serial interface formats.
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
APPLICATION INFORMATION
UDA1360TS
handbook, full pagewidth
Rin
C11 47 F (16 V)
X5
VINL
1
16
VDDA C6 47 F (16 V) C10 100 nF (63 V)
R3 1 VDDA
C3 47 F (16 V)
C7 100 nF (63 V) VSSA
Vref
2
15
VSSA VSSA R7 47 k VDDD X3-1 X3-2 X3-3
Rin X6
C12 47 F (16 V) VSSA
VINR
3
14
FSEL
R6 47 k Vref(n) DATAO
4
13
VSSD X1-1 X1-2 X1-3 X1-4 X1-5 X1-6 X1-7 X1-8 X1-9 X1-10 VSSD
C4 47 F (16 V) R1 VDDA 1 X4
C8 100 nF (63 V) Vref(p) 5
UDA1360TS
12 WS
VSSD VDDD VDDD X2-1 X2-2 X2-3 R4 47 k
SFOR
6
11
BCK
VSSD PWON 7 10 VSSD C5 47 F (16 V) SYSCLK 8 9 VDDD C9 100 nF (63 V) R2 1 VSSD R11
R5 47 k VSSD R10 47
VSSD
L1 BLM32A07 VD L2 BLM32A07 VDDA C1 100 F (16 V) VSSA C2 100 F (16 V) VSSD VDDD
47
MGM971
Fig.5 Application diagram.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
UDA1360TS
SOT369-1
D
E
A X
c y HE vM A
Z
16
9
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
UDA1360TS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable
UDA1360TS
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
NOTES
UDA1360TS
2000 Feb 08
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
NOTES
UDA1360TS
2000 Feb 08
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/02/pp16
Date of release: 2000
Feb 08
Document order number:
9397 750 05031

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